The present invention relates to a PLL (Phase Locked Loop) circuit and an operation method thereof.
A digital PLL circuit using a bang-bang PD (bang-bang phase detector; hereinafter referred to as a BB-PD) as a phase detector is disclosed in IEEE J. Solid-State Circuits, vol. 46, No. 8, AUGUST 2011 “A 0.7-to-3.5 GHz 0.6-to-2.8 mW Highly Digital Phase-Locked Loop With Bandwidth Tracking” (hereinafter referred to as Non Patent Literature 1). The BB-PD outputs detected phase delay/advance information as a 1-bit digital signal. An integral path holds the delay/advance information and controls an IDAC using a holding code DI. A double integral path is also provided.
U.S. Pat. No. 7,999,586 discloses a PLL circuit including a proportional path (proportional path 150) and an integral path (integral path 160). The integral path accumulates output signals from a BB-PD. The proportional path is provided with a gain Ki. The integral path is divided into a proportional-integral path (proportional-integral path 190) and an integral-integral path (integral-integral path 200). The proportional-integral path is provided with a gain Kpi, and the integral-integral path is provided with a gain Kii.
U.S. Pat. No. 8,513,995 discloses a PLL circuit including a fast integral path (fast integral path 46), a slow integral path (slow integral Path 48), and a proportional path (proportional path 60). The fast integral path and the slow integral path are connected to each other through a low-pass filter (LPF 49).
However, the PLL circuits disclosed in the related art described above have a problem that it is difficult to achieve a PLL circuit having a desired performance.
Other problems to be solved by and novel features of the present invention will become apparent from the following description and the accompanying drawings.